1. Field of the Invention
The present invention relates generally to methods for fabricating field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for fabricating, with enhanced performance, field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication, and in particular within the art of semiconductor integrated circuit microelectronic fabrication, to fabricate microelectronic devices, and in particular semiconductor integrated circuit microelectronic devices, such as but not limited to field effect transistor (FET) device semiconductor integrated circuit microelectronic devices, with enhanced performance within decreased microelectronic fabrication substrate area within microelectronic fabrications, and in particular within decreased semiconductor integrated circuit microelectronic fabrication substrate area within semiconductor integrated circuit microelectronic fabrications.
While microelectronic devices fabricated with enhanced performance within decreased microelectronic fabrication substrate area within microelectronic fabrications are clearly desirable in the art of microelectronic fabrication, microelectronic devices fabricated with enhanced performance within decreased microelectronic fabrication substrate area within microelectronic fabrications are nonetheless not readily fabricated entirely without problems within the art of microelectronic fabrication. In that regard, it is often difficult to fabricate microelectronic devices with enhanced performance within decreased microelectronic fabrication substrate area within microelectronic fabrications insofar as microelectronic device performance is often fundamentally compromised within a microelectronic device fabricated within decreased microelectronic fabrication substrate area within a microelectronic fabrication.
It is thus desirable in the art of microelectronic fabrication to provide methods and materials through which there may be fabricated with enhanced performance within microelectronic fabrications microelectronic devices within decreased microelectronic fabrication substrate area within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various microelectronic structures having desirable properties, and methods for fabrication thereof, have been disclosed in the art of microelectronic fabrication.
For example: (1) DiVincenzo et al., in U.S. Pat. No. 5,023,671; and (2) Onda, in U.S. Pat. No. 5,119,151, each disclose a quantum mechanical field effect transistor (FET) device fabricated within a semiconductor integrated circuit microelectronic fabrication to provide a one-dimensional carrier gas flow within a modulation doped quantum well structure within the quantum mechanical field effect transistor (FET) device fabricated within the semiconductor integrated circuit microelectronic fabrication, rather than a more conventional two-dimensional carrier gas flow within the modulation doped quantum well structure within the quantum mechanical field effect transistor (FET) device fabricated within the semiconductor integrated circuit microelectronic fabrication. To realize the foregoing result: (1) DiVincenzo et al. employ when forming the modulation doped quantum well structure: (a) a first layer formed of a comparatively narrow bandgap compound semiconductor material; having formed thereupon (b) a longitudinal edge patterned second layer formed of a comparatively wide bandgap compound semiconductor material; while (2) Onda employs when forming the modulation doped quantum well structure: (a) a first layer formed of a first compound semiconductor material; having formed thereupon (b) a second layer formed of a second compound semiconductor material; in turn having formed thereupon (c) an etch stop layer formed of a third compound semiconductor material; finally in turn having formed thereupon (d) a patterned electron supply layer formed of a fourth compound semiconductor material.
In addition: (1) Sallagoity et al., in “Analysis of Width Edge Effects in Advanced Isolation Schemes for Deep Submicron CMOS Technologies,” IEEE Trans. on Electron Devices, 44(11), November 1996, pp. 1900–05; and (2) and Matsuda et al., in “Novel Corner Rounding Process for Shallow Trench Isolation utilizing MSTS (Micro-Structure Transformation of Silicon), IEEE IEDM 98, pp. 137–40, disclose effects of isolation region to active region semiconductor substrate geometric transition with respect to field effect transistor (FET) device performance for a field effect transistor (FET) device fabricated within an active region of a semiconductor substrate adjoining an isolation region formed within the semiconductor substrate. Both Sallagoity et al. and Matsuda et al. disclose the onset of parasitic effects within such a field effect transistor (FET) device formed within the active region of the semiconductor substrate adjoining the isolation region formed within the semiconductor under conditions where the active region of the semiconductor substrate is formed with a sharp corner adjoining the isolation region formed within the semiconductor substrate, such that rounding of the sharp corner within the active region of the semiconductor substrate is desirable in order to minimize the parasitic effects.
Desirable in the art of microelectronic fabrication are additional methods and materials through which there may be fabricated with enhanced performance within microelectronic fabrications microelectronic devices within decreased microelectronic substrate area within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.